Implemented "full" ignition timing system

This is a first implementation of a "full" timing system, with proper
handling for cases wher the ignition charge time overlaps with the
compression pulse, the spark has a more complex state machine system
with the option to defer charge from the intake pulse to the compression
pulse, and further defferal of the spark release schedule to the ISR
that triggers when the output compare triggers for the charge

Preliminary error counters have been put in place, they still require
handling error conditions that would force a soft shutdown on the
ignition IC. Alongside this the code still needs to be verified so that
all non critical errors (ie missed charge schedules) reset the state
machine and increment a global spark miss counter to avoid having these
errors breaking the state machine as they can easily be recovered from

Cases where the coil would already be charging and an error occurs
require as stated above a full recovery procedure with soft shutdown of
the ignition IC and a clean cycle of the state machine to ensure a full
recovery

STM32/CM7/Core/Inc/FreeRTOSConfig.h

@@ -50,7 +50,6 @@
 #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
 #include <stdint.h>
 extern uint32_t SystemCoreClock;
-void xPortSysTickHandler(void);
 #endif
 #ifndef CMSIS_device_header
 #define CMSIS_device_header "stm32h7xx.h"
@@ -164,7 +163,7 @@ standard names. */
 #define vPortSVCHandler    SVC_Handler
 #define xPortPendSVHandler PendSV_Handler
 /* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */
- #define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 1
+ #define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0
 
 /* USER CODE BEGIN Defines */
 /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */

STM32/CM7/Core/Inc/global_state.h

@@ -7,7 +7,8 @@
 #include <stdint.h>
 
 #define MAX_CAM_MISS 2
-#define SPARK_ADVANCE 40
+#define SPARK_ADVANCE 30
+#define SPARK_CHARGE_TIME 3000
 #define INJECTION_PHASE 0
 
 typedef enum { SYNC_OK = 0, SYNC_PENDING = 1, SYNC_NOT_OK = 2 } sync_state_t;
@@ -24,10 +25,21 @@ typedef enum { CAM_IDLE = 0, CAM_TRIGD = 1 } cam_state_t;
 
 typedef enum {
   SPARK_IDLE = 0,
-  SPARK_CHARGING = 1,
-  SPARK_NONE = 2
+  SPARK_PENDING_CHARGE = 1,
+  SPARK_CHARGING = 2,
+  SPARK_PENDING_RELEASE = 3,
+  SPARK_NONE = 4
 } spark_state_t;
 
+typedef struct {
+  uint32_t overspeed_error_ctr;
+  uint32_t defer_charge_error_ctr;
+  uint32_t revised_charge_error_ctr;
+  uint32_t task_release_error_ctr;
+  uint32_t state_error_ctr;
+  uint32_t isr_release_error_ctr;
+} spark_errors_t;
+
 typedef struct {
   crank_state_t crank_state;
   cam_state_t cam_state;
@@ -37,4 +49,8 @@ typedef struct {
   ring_buffer_t cam_RB;
   spark_state_t next_spark_state;
   spark_state_t current_spark_state;
+  bool charge_defer;
+  bool spark_defer;
+  uint32_t t_defer_spark;
+  spark_errors_t spark_errors;
 } global_state_t;

STM32/CM7/Core/Inc/ring_buffer.h

@@ -8,8 +8,8 @@ typedef struct ring_buffer_t {
   uint8_t w_head;
 } ring_buffer_t;
 
-inline void ringBufferPush(volatile ring_buffer_t *rb, uint32_t value);
+void ringBufferPush(volatile ring_buffer_t *rb, uint32_t value);
 
-inline uint32_t ringBufferRead(volatile ring_buffer_t *rb, uint8_t neg_idx);
+uint32_t ringBufferRead(volatile ring_buffer_t *rb, uint8_t neg_idx);
 
-inline void ringBufferRevert(volatile ring_buffer_t *rb, uint8_t val);
+void ringBufferRevert(volatile ring_buffer_t *rb, uint8_t val);

STM32/CM7/Core/Inc/stm32h7xx_it.h

@@ -52,8 +52,8 @@ void MemManage_Handler(void);
 void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
-void SysTick_Handler(void);
 void TIM2_IRQHandler(void);
+void TIM6_DAC_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
 /* USER CODE END EFP */

STM32/CM7/Core/Inc/timer_utils.h

@@ -0,0 +1,15 @@
+// Copyright (C) 2026 Hector van der Aa <hector@h3cx.dev>
+// Copyright (C) 2026 Association Exergie <association.exergie@gmail.com>
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#pragma once
+#include "stm32h7xx_hal.h"
+#include <stdbool.h>
+
+#define TIM2_CH3_OC_ACTIVE (1U << TIM_CCMR2_OC3M_Pos)
+#define TIM2_CH3_OC_INACTIVE (2U << TIM_CCMR2_OC3M_Pos)
+#define TIM2_CH3_OC_TOGGLE (3U << TIM_CCMR2_OC3M_Pos)
+
+bool timer_safe_to_arm(uint32_t deadline, TIM_HandleTypeDef *tim);
+
+void TIM2_CH3_SetOCMode(uint32_t oc_mode);