h3cx
7502b354dc
This is a first implementation of a "full" timing system, with proper handling for cases wher the ignition charge time overlaps with the compression pulse, the spark has a more complex state machine system with the option to defer charge from the intake pulse to the compression pulse, and further defferal of the spark release schedule to the ISR that triggers when the output compare triggers for the charge Preliminary error counters have been put in place, they still require handling error conditions that would force a soft shutdown on the ignition IC. Alongside this the code still needs to be verified so that all non critical errors (ie missed charge schedules) reset the state machine and increment a global spark miss counter to avoid having these errors breaking the state machine as they can easily be recovered from Cases where the coil would already be charging and an error occurs require as stated above a full recovery procedure with soft shutdown of the ignition IC and a clean cycle of the state machine to ensure a full recovery
16 lines
516 B
C
16 lines
516 B
C
// Copyright (C) 2026 Hector van der Aa <hector@h3cx.dev>
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// Copyright (C) 2026 Association Exergie <association.exergie@gmail.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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#pragma once
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#include "stm32h7xx_hal.h"
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#include <stdbool.h>
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#define TIM2_CH3_OC_ACTIVE (1U << TIM_CCMR2_OC3M_Pos)
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#define TIM2_CH3_OC_INACTIVE (2U << TIM_CCMR2_OC3M_Pos)
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#define TIM2_CH3_OC_TOGGLE (3U << TIM_CCMR2_OC3M_Pos)
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bool timer_safe_to_arm(uint32_t deadline, TIM_HandleTypeDef *tim);
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void TIM2_CH3_SetOCMode(uint32_t oc_mode);
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