[UNVERIFIED] Astra diagram pass
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# Architecture diagram sources
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The architecture Markdown embeds these 22 SVG figures. Matching PNG previews
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are provided for viewers that do not support SVG. Diagrams describe the working
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architecture; component qualification and schematic-release requirements remain
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in the parent documents.
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## Figures
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| Topic | Figures |
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| --- | --- |
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| Power | [Sources](power-sources.svg), [protected branches](power-branches.svg) |
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| Analogue acquisition | [Passive input](analog-input.svg), [thermistor](thermistor.svg), [ratiometric acquisition](ratiometric.svg) |
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| Timing inputs | [Crank/cam interface](trigger-input.svg) |
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| Deadman | [Contacts and diagnostics](deadman-inputs.svg), [permit gates](deadman-permit.svg), [output gates](deadman-outputs.svg) |
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| Ignition | [Power](ignition-power.svg), [commands](ignition-command.svg), [current flag](ignition-flag.svg), [grounding](ignition-ground.svg) |
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| Injection | [Power](injector-power.svg), [command](injector-command.svg), [status](injector-status.svg), [grounding](injector-ground.svg) |
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| Generic outputs | [5 V logic](logic-output.svg), [low-side power](sink-power.svg), [supplies and SPI](sink-interfaces.svg), [command bias](sink-command.svg) |
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| Optional DAC | [Output provision](dac-output.svg) |
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## Editing and regeneration
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- The 12 block figures have editable `.drawio` sources. Open them in draw.io.
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`build_blocks.py` recreates their baseline layout and `block-connections.json`.
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Running it overwrites manual layout edits, so update the generator when those
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edits should be reproducible, or export the edited `.drawio` directly.
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- The 10 circuit/logic figures are generated by `build_circuits.py`, with a
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separate `*.topology.json` connection manifest for each figure. Change the
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relevant component/net definitions and layout together in that script;
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rerunning it overwrites the generated topology and images. JSON is a review
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manifest, not an independently interpreted rendering input.
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- Reference designators introduced by these drawings are documentation labels,
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not KiCad assignments. Named continuation ports are electrically identical
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only when their names match within the documented domain.
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Run from this directory using the configured schematic environment:
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```bash
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python build_blocks.py
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~/.venvs/codex-schematics/bin/python export_blocks.py
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~/.venvs/codex-schematics/bin/python build_circuits.py
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```
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`export_blocks.py` requires the installed draw.io desktop renderer; restricted
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Electron sandboxes may require an authorized external execution. It exports
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only `.drawio` inputs, keeps editable sources, checks for native SVG text, and
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creates PNG previews. The circuit builder uses Schemdraw and CairoSVG.
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Inspect changed figures at their intended embedded size after rebuilding.
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Validate each circuit manifest with the installed topology validator:
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```bash
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~/.venvs/codex-schematics/bin/python \
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~/.codex/skills/electronics-schematic-rendering/scripts/validate_topology.py \
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analog-input.topology.json
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```
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## Source clarifications in this redraw
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- The former power-tree branch labelled `+5V_AUX` after 3.3 V filtering is now
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`+3V3_ANA`, matching the dedicated rail description. `+5V_AUX` remains a
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protected branch of `+5V_MAIN`.
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- The passive ADC drawing now shows `C_HOLD` as a shunt capacitor after the
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small isolation resistor specified in the prose. It does not add a separate
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connector-side `R_PROT`. Exact values remain unspecified.
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- The Hall-input drawing separates sensor supply, sensor return and signal;
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the original ASCII alignment could suggest an unintended join. The pull-up,
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divider and parallel filter follow the existing prose.
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- The deadman equations are unchanged. Contact observations, permission gates
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and output gates occupy separate figures; shared net names connect them.
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- `VBG_LOCAL_KELVIN` labels the documented local ignition reference at the
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`IGN_PGND` joining point. `LOCAL_GND` in the sink-command figure denotes the
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TLE9104SH local ground reference. Neither denotes a new remote ground path.
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- The obsolete reference to a missing figure in `DIGITAL_INPUTS.md` was removed.
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That module remains described by its existing component-level prose.
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Protection blocks whose devices or ratings remain unselected are deliberately
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functional. Supply-loss behavior, real pin mappings, ratings and physical fault
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responses still require the validation specified in the module documents.
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