NeoECU-Firmware/docs/ARCHITECTURE.md

NeoECU Firmware Architecture

AMP

NeoECU features an AMP (Asymmetric Multi Processing) architecture making use of both the CM7 and CM4 core of the STM32H747 MCU powering NeoECU

CM7

The Cortex M7 is in charge of initial boot and more importantly all of the engine control. The core uses the following software stack:

• STM32_HAL
• FreeRTOS
• CMSISv2 This fairly low-level software stack, paired with strict coding rules, allows for stable and deterministic engine control. The key coding rules are:
• No heap allocation
• Pointer indirection limited to one level Further coding rules, guidelines and conventions can be found in CODING.md

CM4

The Cortex M4 handles all of the telemetry, and other vehicle functions. It will be build around ZephyrRTOS to allow for a higher level of abstraction and a complete I/O stack out of the box. The code written for this core will not follow the same rules as for the CM7 as anything run on the CM4 should be non critical to core engine function.

Engine Control

As mentioned previously, all core engine control is handled on the Cortex M7, this is to isolate critical engine control from heavier telemetry operations that are non critical to core engine function.

Input Signals

The engine provides two key input signals:

• Crank pulse
• Cam pulse These are both registered using a hardware interrupt using TIM2 as a low jitter time source.

Time Base

TIM2 is the main timebase used to control the engine, it provides 4 channels that are used as follows:

• CH_1: Crank input compare
• CH_2: Cam input compare
• CH_3: Undefined
• CH_4: Undefined