125 lines
4.1 KiB
Markdown
125 lines
4.1 KiB
Markdown
# NeoECU Target Architecture
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NeoECU uses an AMP layout. The `CM7` side owns deterministic engine control; the secondary core is reserved for non-critical work and is outside the scope of this document.
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This document describes the target `CM7` architecture. Current development-board details and temporary implementation notes live in [`DEVELOPMENT_SETUP.md`](./DEVELOPMENT_SETUP.md).
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## CM7 Role
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`CM7` is responsible for:
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- capturing crank and cam timing edges with low jitter
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- maintaining engine phase synchronization
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- deriving the current four-stroke cycle position
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- scheduling time-critical spark and injection transitions
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- keeping interrupt paths short and deterministic
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The engine-control path should stay small, explicit, and timer-driven.
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## Runtime Flow
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The target runtime model is:
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1. A hardware timer captures crank and cam edges.
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2. The input-capture callback stores each timestamp.
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3. The callback wakes the task that owns that signal.
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4. The task validates the event, updates engine state, and computes future actions.
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5. Output-compare events apply scheduled actuator transitions.
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Interrupt context owns timestamp capture and exact compare-time transitions. Task context owns filtering, state progression, synchronization, and scheduling decisions.
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## Sensors
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### Crank
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The crank signal is the primary timing source.
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- One crank pulse represents `180` engine degrees.
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- Consecutive crank intervals estimate current engine speed.
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- Crank timing drives phase progression and scheduled outputs.
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### Cam
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The cam signal is the phase reference.
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- One cam pulse represents the `720` degree four-stroke cycle.
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- Cam timing is used to establish and recover cycle synchronization.
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- Unexpected or missing cam events reduce or clear phase confidence.
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## Shared State
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The target model uses one compact shared engine state object. It contains:
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- synchronization state
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- crank cycle state
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- cam event state
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- cam miss tolerance
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- recent crank and cam timestamp history
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- scheduled spark state
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State shared between ISR and task context must be explicit. If a value crosses that boundary, its ownership and meaning should be clear from the surrounding code.
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## Synchronization
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Synchronization has three states:
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- `SYNC_NOT_OK`: phase is not trusted
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- `SYNC_PENDING`: cam has been observed, but phase is not confirmed
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- `SYNC_OK`: crank/cam relationship is trusted
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Target progression:
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1. Boot starts unsynchronized.
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2. A cam event moves the system to pending sync.
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3. The expected crank/cam phase relationship promotes sync to OK.
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4. Missing or unexpected cam behavior drops sync back toward unknown phase.
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When synchronized, crank pulses advance through:
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1. `CYCLE_COMBUSTION`
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2. `CYCLE_EXHAUST`
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3. `CYCLE_INTAKE`
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4. `CYCLE_COMPRESSION`
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When unsynchronized, the crank state remains unknown until cam-assisted phase alignment restores confidence.
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## Timing and Scheduling
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Scheduled outputs are derived from recent crank timing.
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The target scheduler should:
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- compute future compare times from measured crank intervals
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- arm hardware compare events instead of busy waiting
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- keep actuator transitions in compare callbacks short and deterministic
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- keep scheduling decisions near the sensor logic that drives them
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Spark and injection should both follow this pattern:
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1. The crank task computes the next transition time.
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2. The timer compare channel is armed.
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3. The compare callback applies the transition.
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4. Follow-up transitions are scheduled by task logic.
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## Core Modules
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The intended `CM7` module boundaries are:
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- `main.c`: boot, peripheral initialization, HAL callbacks, task creation
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- `tasks/crank.c`: crank validation, cycle progression, output scheduling
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- `tasks/cam.c`: cam validation and sync promotion
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- `global_state.h`: shared state, enums, timing constants
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- `ring_buffer.*`: timestamp history
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## Open Target Work
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The current target architecture still needs final decisions or validation for:
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- complete injection scheduling
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- final spark dwell-time handling
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- production crank/cam phase validation
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- sync-loss and recovery thresholds
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- final hardware pin and timer routing
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